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______________________________________________ maxim integrated products 1 some revisions of this device may incorporate deviations from publish ed specifications known as errata. multiple revisions of any device may be simultaneously available through variou s sales channels. for information about device errata, go to: www.maxim - ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1- 888 - 629 - 4642, or visit maxims website at www.maxim - ic.com. ds2 6 9 0 0 j tag m ult iplexe r/sw it ch ge ne ra l de sc ript ion the ds26900 is a jtag signal multiplexer providing connectivity between one of three master ports and up to 18 (36 in cascade configuration) secondary ports. the device is fully configurable from any one of the three master ports. the ds26900 can automatically detect the presence jtag devices on the secondary ports. the ds26900 can be used in multiple configurations including as a single device, two cascaded devices, or two redundant devices. all device control and configuration is accomplished through standard jtag operations via the selected master port. applic a t ions microtca? chassis atca ? chassis amc carrier cards jsm modules system level jtag m ic rot ca j sm func t iona l dia g ra m amc1 ds26900 jtag switch amc2 amc3 amc4 amc18 amcn mch1 mch2 craft master1 master3 master2 fe a t ure s ? efficient solution for star architecture jtag ? provides transparent communications between the arbitrated master and a selected secondary port ? single - package solution provides 18 secondary ports ? two - package cas cade configuration provides 36 secondary ports ? three arbitrated master ports ? autodetection of port presence ? internal pullup/down resistors ? two 32 - bit scratchpad registers ? four gpio pins for read/write control and signaling applications ? operation up to 50m hz ? signal path modification options ? redundancy with high - impedance pin ? independent periphery jtag ? configuration mode uses ieee 1149.1 tap controller ? supports live insertion/withdrawal ? 3.3v operation ? industrial temperature operation ? rohs - compliant packaging orde ring i nform a t ion part temp range pin - package ds26900 l n+ - 40 c to +85 c 144 lqfp + denotes a lead (pb) - free/rohs - compliant package. 19 - 5747; rev 1; 2/11 microtca and atca are registered trademarks of picmg. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 2 t a ble of cont e nt s 1. block diagram ........................................................................................................................ 6 2. pin descriptions ..................................................................................................................... 7 3. functional descripti on .................................................................................................... 19 4. detailed descrip tion .......................................................................................................... 20 4.1 m odes of o peration ............................................................................................................... 20 4.1.1 single - package mode ..................................................................................................................... 20 4 .1.2 cascade configuration modes ........................................................................................................ 21 4.1.3 deselect mode and redundancy ..................................................................................................... 22 4.2 m aster a rbitration ................................................................................................................ 23 4.2.1 missing test master or unused test master port ............................................................................ 24 4.2.2 detection of the presence of secondary ports ................................................................................. 24 4.2.3 selection of the secondary port ...................................................................................................... 24 4.2.4 master port/secondary port path timing description ...................................................................... 24 4.3 gpio p ins g eneral -p urpose i/o ......................................................................................... 25 4.4 p rogrammable p ullup /p ulldown r esistors ........................................................................ 25 4.5 s ignal p ath c onfiguration i nversions .............................................................................. 25 4.6 s witch c onfiguration by e xternal t est m aster ................................................................ . 25 4.7 s witch c onfiguration by t est m aster 1 or t est m aster 2 ................................................. 26 5. resets ...................................................................................................................................... 27 5.1 g lobal r eset u sage ............................................................................................................... 27 5.2 s econdary p ort r esets ........................................................................................................ 27 6. configuration mode ........................................................................................................... 28 6.1 s witch tap c ontroller ......................................................................................................... 28 6.1.1 switch instructions .......................................................................................................................... 28 7. device registers .................................................................................................................. 31 8. additional applicati on information ............................................................................ 37 8 .1 a ccessing i ndividual d evice jtag on a b oard ..................................................................... 37 8.2 u sing led i ndicators on the sspi , a ct and mc i p ins .......................................................... 37 8.3 u sing 2.7v and 1 .8v l ogic l evels with the ds26900 ............................................................ 37 8.4 s eries t ermination r esistors ............................................................................................... 37 9. periphery jtag ...................................................................................................................... 38 9.1 p eriphery jtag d escription ................................................................................................ . 38 9.2 jtag tap c ontroller s tate m achine d escription ............................................................. 39 9.3 jtag i n struction r egister and i nstructions ...................................................................... 41 9.3.1 sample/preload ....................................................................................................................... 41 9.3.2 extest ......................................................................................................................................... 41 9.3.3 bypass ......................................................................................................................................... 41 9.3.4 idcode ......................................................................................................................................... 41 9.3.5 highz ............................................................................................................................................ 41 9.3.6 clamp ........................................................................................................................................... 42 9.4 jtag t est r egisters .............................................................................................................. 42 9.4.1 bypass register .............................................................................................................................. 42 9.4.2 identification register ...................................................................................................................... 42 9.4.3 boundary scan register ................................................................................................................. 42 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 3 10. operating parameters ...................................................................................................... 43 10.1 t hermal i nformation ........................................................................................................... 43 10.2 dc c haracteristics ............................................................................................................ 43 11. ac timing .................................................................................................................................. 44 11.1 s witch tap c ontroller i nterface t iming ......................................................................... 44 11.2 t ransparent m ode m aster /s lave p ort t iming ................................................................ . 45 11.3 p eriphery jtag i nterface t iming ...................................................................................... 46 12. pin configuration ................................................................................................................ 47 13. package information ......................................................................................................... 48 14. document revision hi story ............................................................................................. 49 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 4 list of figure s figure 1 - 1. ds26900 block diagram ...................................................................................................................... 6 figure 4 - 1. configuration for 3 masters, 18 secondary ports ................................................................................ 20 figure 4 - 2. configuration for 1 master, 20 secondary ports .................................................................................. 20 figure 4 - 3. two cascaded devices ...................................................................................................................... 21 figure 4 - 4. three cascaded devices using external select logic ........................................................................ 22 figure 9 - 1. periphery jtag block diagr am .......................................................................................................... 38 figure 9 - 2. jtag tap controller state machine .................................................................................................. 39 figure 11 - 1. switch tap controller interface timing diagram .............................................................................. 44 figure 11 - 2. transparent mode master/slave port timing diagram ...................................................................... 45 figure 11 - 3. periphery jtag interface timing diagram ....................................................................................... 46 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 5 list of t a ble s table 2 - 1. pin descriptions (sorted by function) .................................................................................................... 7 table 2 - 2. pin description (sorted by pin number) .............................................................................................. 13 table 4 - 1. mode pins ........................................................................................................................................... 20 table 4 - 2. master arbitration ................................................................................................................................ 23 table 4- 3. act output states .............................................................................................................................. 24 table 6 - 1. switch tap instruction codes ............................................................................................................. 28 table 7 - 1. ds26900 list of registers ................................................................................................................... 31 table 7 - 2. secondary port selection bits and indicator pins ................................................................................. 35 table 9 - 1. periphery jtag instruction codes ....................................................................................................... 41 table 10 - 1. thermal characteristics ..................................................................................................................... 43 table 10 - 2. recommended dc operating conditions .......................................................................................... 43 table 10 - 3. dc electrical characteristics ............................................................................................................. 43 table 11 - 1. switch tap controller interface timing ............................................................................................. 44 table 11 - 2. master/slave port timing .................................................................................................................. 45 table 11 - 3. periphery jtag interface timing ....................................................................................................... 46 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 6 1 . bloc k dia gra m figure 1-1 . ds26900 block diagram secondary 1 secondary 2 secondary 3 secondary 4 secondary 18 port mux switch logic switch tap controller periphery tap controller master arbiter register bank external test port test master port 1 gpio [3:0] sspi [4:0] prog inversions mode [1:0] jtag 5 act mci mgnt test master port 2 6 6 6 ds26900 55 5 5 5 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 7 2 . pin de sc ript ions table 2-1 . pin descriptions (sorted by function) name pin type function etck 4 ipd external test master clock. in configuration mode, a falling edge on this pin clocks data in on the etdi pin. a falling edge on this pin clocks data out on the etdo pin. when pren = v dd , a 20k ? pulldown resistor is connected to this pin. etdi 2 ipd external test master serial data input. in configuration mode, data is clocked in on this pin on the falling edge of etck. when pren = v dd , a 20k ? pulldown resistor is connected to this pin. etdo 3 o/ high impedance external test master serial data out. (high impedance) data is clocked out on this pin on the falling edge of etck. when pren = v dd , a 10k ? pullup resistor is connected to this pin. ecfg 5 ipu external test master configuration (active low). asserting this pin low along with ereq asserted low allows the external test master to configure the ds26900, allowing access to the switch tap controller. toggling ecfg when ereq is high has no effect. when pren = v dd , a 10k ? pullup resistor is connected to this pin. etms 6 ipu external test master test mode select. this pin is sampled on the rising edge of etck and is used to place the port into the various defined ieee 1149.1 states. when pren = v dd , a 10k ? pullup resistor is connected to this pin. ereq 1 ipu external test master request (active low). (internal 10k ? pullup) when active, this pin selects the external test port as the master. whe n switching ereq , none of the master clocks should be toggling. mgnt0 144 o master grant 0 (active low). asserted low when the external test master is the arbitrated master. tck1 22 ipd/o test master 1 test port clock master mode = input slave mode = o utput when pren = v dd , an internal 20k ? pulldown resistor is connected to this pin. tdi1 20 ipu/o test master 1 test port serial data input master mode = input slave mode = output when pren = v dd , an internal 10k ? pullup resistor is connected to this p in. tdo1 21 i/o test master 1 test port serial data out master mode = output slave mode = input when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. trst1 23 ipu/o test master 1 test port test reset (active low). asserting this p in low (when master) puts the ds26900 into configuration mode, allowing access to the switch tap controller. toggling trst1 when not the arbitrated master has no effect. this pin does not directly affect secondary port resets. master mode = trst1 input sl ave mode = trst1 output when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 8 name pin type function tms1 24 ipd/o test master 1 test port test mode select master mode = input slave mode = output when pren = v dd , an internal 20k ? pulldown resistor is conn ected to this pin. tmreq1 19 ipu test master 1 master request (active low). (internal 10k ? pullup) when ereq is inactive and tmreq1 is active, this pin selects the test master port 1 as the mast er. when switching tmreq1 , none of the master clocks should be toggling. mgnt1 18 o master grant 1 (active low). asserted low when test master 1 is the arbitrated master. tck2 30 ipd/o test master 2 test port clock master mode = input slave mode = output when pren = v dd , an internal 20k ? pulldown resistor is con nected to this pin. tdi2 28 ipu/o test master 2 test port serial data input master mode = input slave mode = output when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. tdo2 29 i/o test master 2 test port serial data out master mo de = output slave mode = input when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. trst2 31 ipu/o test master 2 test port test reset (active low). asserting this pin low (when master) puts the ds26900 into configuration mode, allo wing access to the switch tap controller. toggling trst2 when not the arbitrated master has no effect. this pin does not directly affect secondary port resets. master mode = trst2 input slave mode = trst2 output when pren = v dd , an internal 10k ? pullup r esistor is connected to this pin. tms2 32 ipd/o test master 2 test port test mode select master mode = input slave mode = output when pren = v dd , an internal 20k ? pulldown resistor is connected to this pin. tmreq2 27 ipu test master 2 master request (a ctive low) (internal 10k ? pullup) when ereq and tmreq1 are inactive and tmreq2 is active, this pin selects the test master port 2 as the master. when switching tmreq2 , none of the master clocks should be toggling. mgnt2 25 o master grant 2 (active low). asserted low when test master 2 is the arbitrated master. stck1 91 o secondary port 1 test clock stdi1 92 o secondary port 1 serial data in stdo1 93 ipu secondary port 1 serial data out (internal 10k ? pullup) strst1 90 o secondary port 1 test reset (a ctive low) stms1 89 o secondary port 1 test mode select (internal 20k ? pulldown) stck2 86 o secondary port 2 test clock stdi2 87 o secondary port 2 serial data input stdo2 88 ipu secondary port 2 serial data out (internal 10k ? pullup) strst2 85 o seco ndary port 2 test reset (active low) downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 9 name pin type function stms2 84 o secondary port 2 test mode select (internal 20k ? pulldown) stck3 80 o secondary port 3 test clock stdi3 81 o secondary port 3 serial data input stdo3 82 ipu secondary port 3 serial data out (internal 10k ? pullup) strst3 79 o secondary port 3 test reset (active low) stms3 78 o secondary port 3 test mode select (internal 20k ? pulldown) stck4 75 o secondary port 4 test clock stdi4 76 o secondary port 4 serial data input stdo4 77 ipu secondary port 4 seri al data out (internal 10k ? pullup) strst4 74 o secondary port 4 test reset (active low) stms4 73 o secondary port 4 test mode select (internal 20k ? pulldown) stck5 70 o secondary port 5 test clock stdi5 71 o secondary port 5 serial data input stdo5 72 ipu secondary port 5 serial data out (internal 10k ? pullup) strst5 69 o secondary port 5 test reset (active low) stms5 68 o secondary port 5 test mode select (internal 20k ? pulldown) stck6 65 o secondary port 6 test clock stdi6 66 o secondary port 6 s erial data input stdo6 67 ipu secondary port 6 serial data out (internal 10k ? pullup) strst6 64 o secondary port 6 test reset (active low) stms6 63 o secondary port 6 test mode select (internal 20k ? pulldown) stck7 59 o secondary port 7 test clock std i7 60 o secondary port 7 serial data input stdo7 61 ipu secondary port 7 serial data out (internal 10k ? pullup) strst7 58 o secondary port 7 test reset (active low) stms7 57 o secondary port 7 test mode select (internal 20k ? pulldown) stck8 54 o second ary port 8 test clock stdi8 55 o secondary port 8 serial data input stdo8 56 ipu secondary port 8 serial data out (internal 10k ? pullup) strst8 53 o secondary port 8 test reset (active low) stms8 52 o secondary port 8 test mode select (internal 20k ? pu lldown) stck9 49 o secondary port 9 test clock stdi9 50 o secondary port 9 serial data input stdo9 51 ipu secondary port 9 serial data out (internal 10k ? pullup) strst9 47 o secondary port 9 test reset (active low) stms9 46 o secondary port 9 test mod e select (internal 20k ? pulldown) stck10 43 o secondary port 10 test clock stdi10 44 o secondary port 10 serial data input stdo10 45 ipu secondary port 10 serial data out (internal 10k ? pullup) strst10 42 o secondary port 10 test reset (active low) st ms10 41 o secondary port 10 test mode select (internal 20k ? pulldown) downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 10 name pin type function stck11 138 o secondary port 11 test clock stdi11 139 o secondary port 11 serial data input stdo11 140 ipu secondary port 11 serial data out (internal 10k pullup) strst11 137 o second ary port 11 test reset (active low) stms11 136 o secondary port 11 test mode select (internal 20k ? pulldown) stck12 132 o secondary port 12 test clock stdi12 134 o secondary port 12 serial data input stdo12 135 ipu secondary port 12 serial data out (in ternal 10k ? pullup) strst12 131 o secondary port 12 test reset (active low) stms12 130 o secondary port 12 test mode select (internal 20k ? pulldown) stck13 127 o secondary port 13 test clock stdi13 128 o secondary port 13 serial data input stdo13 129 ipu secondary port 13 serial data out (internal 10k ? pullup) strst13 126 o secondary port 13 test reset (active low) stms13 125 o secondary port 13 test mode select (internal 20k ? pulldown) stck14 122 o secondary port 14 test clock stdi14 123 o seconda ry port 14 serial data input stdo14 124 ipu secondary port 14 serial data out (internal 10k ? pullup) strst14 121 o secondary port 14 test reset (active low) stms14 120 o secondary port 14 test mode select (internal 20k ? pulldown) stck15 116 o secondary port 15 test clock stdi15 117 o secondary port 15 serial data input stdo15 118 ipu secondary port 15 serial data out (internal 10k ? pullup) strst15 115 o secondary port 15 test reset (active low) stms15 114 o secondary port 15 test mode select (intern al 20k ? pulldown) stck16 111 o secondary port 16 test clock stdi16 112 o secondary port 16 serial data input stdo16 113 ipu secondary port 16 serial data out (internal 10k pullup) strst16 110 o secondary port 16 test reset (active low) stms16 109 o se condary port 16 test mode select (internal 20k ? pulldown) stck17 105 o secondary port 17 test clock stdi17 106 o secondary port 17 serial data input stdo17 107 ipu secondary port 17 serial data out (internal 10k ? pullup) strst17 104 o secondary port 17 test reset (active low) stms17 103 o secondary port 17 test mode select (internal 20k ? pulldown) stck18 100 o secondary port 18 test clock stdi18 101 o secondary port 18 serial data input stdo18 102 ipu secondary port 18 serial data out (internal 10k ? pullup) strst18 99 o secondary port 18 test reset (active low) stms18 98 o secondary port 18 test mode select (internal 20k ? pulldown) n.c. 94, 95 no connection downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 11 name pin type function sspi4 8 o selected secondary port indicator bit 4 (active low). along with pins sspi3 , s spi2 , sspi1, and sspi0 , this pin provides a hardware indication of the selected secondary port. see table 7-2 for more information. sspi3 9 o selected secondary port indicator bit 3 (active low). along wi th pins sspi4 , sspi2 , sspi1, and sspi0 , this pin provides a hardware indication of the selected secondary port. see table 7 - 2 for more information. sspi2 10 o selected secondary port indicator bit 2 (acti ve low). along with pins sspi4 , sspi3 , sspi1, and sspi0 , this provides a hardware indication of the selected secondary port. see table 7 - 2 for more information. sspi1 11 o selected secondary port indicato r bit 1 (active low). along with pins sspi4 , sspi3 , sspi2, and sspi0 , this pin provides a hardware indication of the selected secondary port. see table 7 - 2 for more information. sspi0 12 o selected second ary port indicator bit 0 (active low). along with pins sspi4 , sspi3 , sspi2, and sspi1 , this pin provides a hardware indication of the selected secondary port. see table 7 - 2 for more information. gpio[3] 14 ipd/o general - purpose input/output bit 3. (internal 20k ? pulldown) this pin is a general - purpose input/output, which can be read or driven via a register bit. this pin is in input mode after a global reset. gpio[2] 15 ipd/o general - purpose input/output bit 2. (internal 20k ? pulldown) this pin is a general - purpose input/output, which can be read or driven via a register bit. this pin is in input mode after a global reset. gpio[1] 16 ipd/o general - purpose input/output bit 1. (internal 20k ? pulldown) this pin is a general - purpose input/output, which can be read or driven via a register bit. this pin is in input mode after a global reset. gpio[0] 17 ipd/o general - purpose input/output bit 0. (internal 20k ? pulldown) this pin is a general - purpose input/output , which can be read or driven via a register bit. this pin is in input mode after a global reset. rst 33 ipu global reset (active low). (internal 10k ? pullup) a low state on this pin provides an asynchronous reset for global registers and logic. rst shoul d be tied high for normal operation. test 62 ipu test enable (active low). (internal 10k ? pullup) factory test input. test must be tied high or unconnected for normal operation. hiz 143 i output high - impedance enable (active low). when this pin is assert ed low, internal pullup and pulldown resistors are disabled, all outputs are put into high - impedance mode, and master request inputs ( ereq , tmreq1 , tmreq2 ) are disabled. ptrst must also be asserted logic 0. m[1] 141 ipd mode select bit 1. (internal 20k ? pulldown) selects mode of operation of the device (single - package, cascade - master, cascade - extension, or deselect. m[0] 142 ipd mode select bit 0. (internal 20k ? pulldown) selects mode of operation of the device (single - package, cascade - master, cascade - ex tension, or deselect). mci 34 o master conflict indicator (active low). indicates that more than one device is requesting to be master. asserted low when more than one of the ereq, tmreq1, or tmreq2 signals is asserted low. dpdv 96 o deselected port data value. this pin directly indicates the state of the dpdv bit in the device configuration register ( dcr ). ptck 40 i periphery jtag chain test clock. this input must be driven to a logic level during normal operation. pt di 39 i periphery jtag chain serial data input. this input must be driven to a logic level during normal operation. ptdo 38 o periphery jtag chain serial data out downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 12 name pin type function ptrst 37 i periphery jtag chain test reset (active low). during normal operation, this sig nal is asserted low. ptms 35 ipu periphery jtag chain test mode select. this input must be driven to a logic level during normal operation. act 97 o active (active low). indicates that this device is active when low. an active devi ce is determined by the msb of the instruction code and the state of the mode pins m0 and m1. pren 7 i pull - resistor enable. when connected to v dd , the following pull resistors are enabled: 20k ? pulldown on tck1, tck2, etdi, etck, tms1, tms2 10k ? pullup on tdi1, tdi2, etdo, td o1, tdo2, trst1 , trst2 , ecfg , etms when connected to v ss , the pull resistors on the signals above are disabled. when multiple devices are connected in parallel only one device sho uld have pren connected = v dd . v dd 13, 36, 83, 119 p positive supply. 3.3v 5%. all v dd signals should be tied together. v ss 26, 48, 108, 133 p ground reference. all v ss signals should be tied together. configuration mode. the master is communicating with the switch tap controller in the ds2690 0. transparent mode. the master i s communicating directly with the selected secondary port. all pins are i/o in periphery jtag mode except the test , tmreq1 , tmreq2 , ereq , m1, m0, hiz , rst , ptrst , ptck, ptdi, ptdo, and ptms pins. all outputs are rated at 8ma. unused inputs must be tied to logic 1 or 0 if not used and a pullup/pulldown is not present. o = output i = input ipu = input with an internal pullup ipd = input with an internal pulldown p = power downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 13 table 2-2 . pin description (sor ted by pin number) name pin type function ereq 1 ipu external test master request (active low). (internal 10k ? pullup) when active, this pin selects the external test port as the master. when switchin g ereq , none of the master clocks should be toggling. etdi 2 ipd external test master serial data input. in configuration mode, data is clocked in on this pin on the falling edge of etck. when pren = v dd , a 20k ? pulldown resistor is connected to this pin. etdo 3 o/ high impedance external test master serial data out. (high impedance ) data is clocked out on this pin on the falling edge of etck. when pren = v dd , a 10k ? pullup resistor is connected to this pin. etck 4 ipd external test master clock. in configuration mode, a falling edge on this pin clocks data in on the etdi pin. a falling edge on this pin clocks data out on the etdo pin. when pren = v dd , a 20k ? pulldown resistor is connected to this pin. ecfg 5 ipu external test master configuration (active low). asserting this pin low along with ereq assert ed low allows the external test master to configure the ds26900, allowing access to the switch tap controller. toggling ecfg when ereq is high has no effect. when pren = v dd , a 10k ? pullup resistor is connected to this pin. etms 6 ipu external test master test mode select. this pin is sampled on the rising edge of etck and is used to place the port into the various defined ieee 1149.1 states. when pren = v dd , a 10k ? pullup resistor is connected to this pin. pren 7 i pull - resistor enable. when connected t o v dd , the following pull resistors are enabled: 20k ? pulldown on tck1, tck2, etdi, etck, tms1, tms2 10k ? pullup on tdi1, tdi2, etdo, tdo1, tdo2, trst1 , trst2 , ecfg , etms when connected to v ss , the pull resistors on the signals above are disabled. when mu ltiple devices are connected in parallel only one device should hav e pren connected = v dd . sspi4 8 o selected secondary port indicator bit 4 (active low). along with pins sspi3 , sspi2 , sspi1 and sspi0 , provides a hardware indication of the selected second ary port. see table 7 - 2 for more information. sspi3 9 o selected secondary port indicator bit 3 (active low). along with pins sspi4 , sspi2 , sspi1 and sspi0 , provides a hardware indication of the selected secondary port. see table 7 - 2 for more information. sspi2 10 o selected secondary port indicator bit 2 (active low). along with pins sspi4 , sspi3 , sspi1 and sspi0 , provides a hardware indication of the selected secondary port. see table 7 - 2 for more information. sspi1 11 o selected secondary port indicator bit 1 (active low). along with pins sspi4 , sspi3 , sspi2 and sspi0 , provides a hardware indication of the selected secondary port. see table 7 - 2 for more information. sspi0 12 o selected secondary port indicator bit 0 (active low). along with pins sspi4 , sspi3 , sspi2 and sspi1 , provides a hardware indica tion of the selected secondary port. see table 7 - 2 for more information. v dd 13, 36, 83, 119 p positive supply. 3.3v 5%. all v dd signals should be tied together. gpio[3] 14 ipd/o general - purpose input/o utput bit 3. (internal 20k ? pulldown) this pin is a general - purpose input/output, which can be read or driven via a register bit. this pin is in input mode after a global reset. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 14 name pin type function gpio[2] 15 ipd/o general - purpose input/output bit 2. (internal 20k ? pulldown) this pin is a general - purpose input/output, which can be read or driven via a register bit. this pin is in input mode after a global reset. gpio[1] 16 ipd/o general - purpose input/output bit 1. (internal 20k ? pulldown) this pin is a general - purpose input/ output, which can be read or driven via a register bit. this pin is in input mode after a global reset. gpio[0] 17 ipd/o general - purpose input/output bit 0. (internal 20k ? pulldown) this pin is a general - purpose input/output, which can be read or driven v ia a register bit. this pin is in input mode after a global reset. mgnt1 18 o master grant 1 (active low). asserted low when test master 1 is the arbitrated master. tmreq1 19 ipu test master 1 master request (active low). (internal 10k ? pullup) when ereq is inactive and tmreq1 is active, this pin selects the test master port 1 as the mast er. when switching tmreq1 , none of the master clocks should be toggling. tdi1 20 ipu/o test master 1 test port serial data input master mode = input slave mode = output when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. tdo1 21 i/o test master 1 test port serial data out master mode = output slave mode = input when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. tck1 22 ipd/o test master 1 test port clock master mode = input slave mode = output when pren = v dd , an internal 20k ? pulldown resistor is connected to this pin. trst1 23 ipu / o test master 1 test port test reset (active low). asserting this pin low (when mast er) puts the ds26900 into configuration mode, allowing access to the sw itch tap controller. toggling trst1 when not the arbitrated master has no effect. this pin does not directly affect secondary port resets. master mode = trst1 input slave mode = trst1 output when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. tms1 24 ipd/o test master 1 test port test mode select master mode = input slave mode = output when pren = v dd , an internal 20k ? pulldown resistor is connected to this pin . mgnt2 25 o master grant 2 (active low). asserted low when test master 2 is the arbitrated master. v ss 26, 48, 108, 133 p ground reference. all v ss signals should be tied together. tmreq2 27 ipu test master 2 master request (active low). (internal 10k ? pullup) when ereq and tmreq1 are inactive and tmreq2 is active, this pin selects the test master port 2 as the master. when switching tmreq2 , none of the master clocks should be toggling. tdi2 28 ipu/o test master 2 test port serial data input master m ode = input slave mode = output when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 15 name pin type function tdo2 29 i/o test master 2 test port serial data out master mode = output slave mode = input when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. tck2 30 ipd/o test master 2 test port clock master mode = input slave mode = output when pren = v dd , an internal 20k ? pulldown resistor is connected to this pin. trst2 31 ipu/o test master 2 test port test reset (active low). as serting this pin low (when master) puts the ds26900 into configuration mode, allowing access to the switch tap controller. toggling trst2 when not the arbitrated master has no effect. this pin does not directly affect secondary port resets. master mode = trst2 input slave mode = trst2 output when pren = v dd , an internal 10k ? pullup resistor is connected to this pin. tms2 32 ipd/o test master 2 test port test mode select master mode = input slave mode = output when pren = v dd , an internal 20k ? pulldown resistor is connected to this pin. rst 33 ipu global reset (active low). (internal 10k ? pullup) a low state on this pin provides an asynchronous reset for global registers and logic. rst should be tied high for normal operation. mci 34 o master conflict indicator (active low). indicates that more than one device is requesting to be master. asserted low when more than one of the ereq, tmreq1, or tmreq2 signals is asserted low. ptms 35 ipu periphery jtag chain test mode select. this input must be driven to a logic level during normal operation. ptrst 37 i periphery jtag chain test reset (active low). during normal operation, this signal is asserted low. ptdo 38 o periphery jtag chain serial data out ptdi 39 i periphery jtag chain serial data input. this input must be driven to a logic level during normal operation. ptck 40 i periphery jtag chain test clock. this input must be driven to a logic level during normal operation. stms10 41 o secondary port 10 test mode select (internal 20k ? pulldown) strst1 0 42 o secondary port 10 test reset (active low) stck10 43 o secondary port 10 test clock stdi10 44 o secondary port 10 serial data input stdo10 45 ipu secondary port 10 serial data out (internal 10k ? pullup) stms9 46 o secondary port 9 test mode selec t (internal 20k ? pulldown) strst9 47 o secondary port 9 test reset (active low) stck9 49 o secondary port 9 test clock stdi9 50 o secondary port 9 serial data input stdo9 51 ipu secondary port 9 serial data out (internal 10k ? pullup) stms8 52 o second ary port 8 test mode select (internal 20k ? pulldown) strst8 53 o secondary port 8 test reset (active low) downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 16 name pin type function stck8 54 o secondary port 8 test clock stdi8 55 o secondary port 8 serial data input stdo8 56 ipu secondary port 8 serial data out (internal 10k ? pullup) stms7 57 o secondary port 7 test mode select (internal 20k ? pulldown) strst7 58 o secondary port 7 test reset (active low) stck7 59 o secondary port 7 test clock stdi7 60 o secondary port 7 serial data input stdo7 61 ipu secondary port 7 seria l data out (internal 10k ? pullup) test 62 ipu test enable (active low). (internal 10k ? pullup) factory test input. test must be tied high or unconnected for normal operation. stms6 63 o secondary port 6 test mode select (internal 20k ? pulldown) strst6 64 o secondary port 6 test reset (active low) stck6 65 o secondary port 6 test clock stdi6 66 o secondary port 6 serial data input stdo6 67 ipu secondary port 6 serial data out (internal 10k ? pullup) stms5 68 o secondary port 5 test mode select (interna l 20k ? pulldown) strst5 69 o secondary port 5 test reset (active low) stck5 70 o secondary port 5 test clock stdi5 71 o secondary port 5 serial data input stdo5 72 ipu secondary port 5 serial data out (internal 10k ? pullup) stms4 73 o secondary port 4 test mode select (internal 20k ? pulldown) strst4 74 o secondary port 4 test reset (active low) stck4 75 o secondary port 4 test clock stdi4 76 o secondary port 4 serial data input stdo4 77 ipu secondary port 4 serial data out (internal 10k ? pullup) s tms3 78 o secondary port 3 test mode select (internal 20k ? pulldown) strst3 79 o secondary port 3 test reset (active low) stck3 80 o secondary port 3 test clock stdi3 81 o secondary port 3 serial data input stdo3 82 ipu secondary port 3 serial data out (internal 10k ? pullup) stms2 84 o secondary port 2 test mode select (internal 20k ? pulldown) strst2 85 o secondary port 2 test reset (active low) stck2 86 o secondary port 2 test clock stdi2 87 o secondary port 2 serial data input stdo2 88 ipu second ary port 2 serial data out (internal 10k ? pullup) stms1 89 o secondary port 1 test mode select (internal 20k ? pulldown) strst1 90 o secondary port 1 test reset (active low) stck1 91 o secondary port 1 test clock stdi1 92 o secondary port 1 serial data in stdo1 93 ipu secondary port 1 serial data out (internal 10k ? pullup) n.c. 94, 95 no connection dpdv 96 o deselected port data value. this pin directly indicates the state of the dpdv bit in the device configuration register ( dcr ). downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 17 name pin type function act 97 o active (active low). indicates that this device is active when low. an active devi ce is determined by the msb of the instruction code and the state of the m0, m1 mode pins. stms18 98 o secondary port 18 test mode select (intern al 20k ? pulldown) strst18 99 o secondary port 18 test reset stck18 100 o secondary port 18 test clock stdi18 101 o secondary port 18 serial data input stdo18 102 ipu secondary port 18 serial data out (internal 10k ? pullup) stms17 103 o secondary port 17 test mode select (internal 20k ? pulldown) strst17 104 o secondary port 17 test reset (active low) stck17 105 o secondary port 17 test clock stdi17 106 o secondary port 17 serial data input stdo17 107 ipu secondary port 17 serial data out (internal 1 0k ? pullup) stms16 109 o secondary port 16 test mode select (internal 20k ? pulldown) strst16 110 o secondary port 16 test reset (active low) stck16 111 o secondary port 16 test clock stdi16 112 o secondary port 16 serial data input stdo16 113 ipu seco ndary port 16 serial data out (internal 10k ? pullup) stms15 114 o secondary port 15 test mode select (internal 20k ? pulldown) strst15 115 o secondary port 15 test reset (active low) stck15 116 o secondary port 15 test clock stdi15 117 o secondary port 15 serial data input stdo15 118 ipu secondary port 15 serial data out (internal 10k ? pullup) stms14 120 o secondary port 14 test mode select (internal 20k ? pulldown) strst14 121 o secondary port 14 test reset (active low) stck14 122 o secondary port 14 test clock stdi14 123 o secondary port 14 serial data input stdo14 124 ipu secondary port 14 serial data out (internal 10k ? pullup) stms13 125 o secondary port 13 test mode select (internal 20k ? pulldown) strst13 126 o secondary port 13 test reset (ac tive low) stck13 127 o secondary port 13 test clock stdi13 128 o secondary port 13 serial data input stdo13 129 ipu secondary port 13 serial data out (internal 10k ? pullup) stms12 130 o secondary port 12 test mode select (internal 20k ? pulldown) strst 12 131 o secondary port 12 test reset (active low) stck12 132 o secondary port 12 test clock stdi12 134 o secondary port 12 serial data input stdo12 135 ipu secondary port 12 serial data out (internal 10k ? pullup) stms11 136 o secondary port 11 test mo de select (internal 20k ? pulldown) strst11 137 o secondary port 11 test reset (active low) stck11 138 o secondary port 11 test clock stdi11 139 o secondary port 11 serial data input stdo11 140 ipu secondary port 11 serial data out (internal 10k ? pullup ) downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 18 name pin type function m[1] 141 ipd mode select bit 1. (internal 20k ? pulldown) selects mode of operation of the device (single - package, cascade - master, cascade - extension, or deselect). m[0] 142 ipd mode select bit 0. (internal 20k ? pulldown) selects mode of operation of the device (single - package, cascade - master, cascade - extension, or deselect). hiz 143 i output high - impedance enable (active low). when this pin is asserted low, internal pullup and pulldown resistors are disabled, all outputs are put into high impedance mode , and master request inputs ( ereq , tmreq1 , tmreq2 ) are disabled. ptrst must also be asserted logic 0. mgnt0 144 o master grant 0 (active low). asserted low when the external test master is the arbitrated master. configuration mode. the master is communicating with the switch tap controller in the ds2690 0. transparent mode. the master is communicating directly with the selected secondary port . all pins are i/o in periphery jtag mode except the test , tmreq1 , tmreq2 , ereq , m1, m0, hiz , rst , ptrst , ptck, ptdi, ptdo, and ptms pins. all outputs are rated at 8ma. unused inputs must be tied to logic 1 or 0 if not used and a pullup/pulldown is not present. o = output i = input ipu = input with an internal pullup ipd = input with an internal pulldown p = power downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 19 3 . func t iona l de sc ript ion the ds26900 is a star (radial) configuration system - level jtag signal multiplexer, which provides connectivity between a master port and secondary ports. the master port, which has been granted control of the switch, can als o treat the unselected master ports as secondary ports. there are three possible master ports: etm (external test master), tm1 (test master 1), and tm2 (test master 2). etm functions as the primary master with tm1 and tm2 available as alternative masters. direct arbitration determines which of the three possible masters can control the switch. etm has the highest priority w henever there is a conflict over which master port can control the device. see section 4.2 for more information on master port arbitration. jtag connectivity is provided for up to 18 secondary ports per package as well as two additional secondary ports, tm1 and tm2, when they are not functioning as a master. two ds26900s can be cascaded to provide additional secondary ports. the ds26900 can be in one of four modes: single - package mode, cascade - master mode, cascade - extension mode, and deselect mode. the ds26900 contains two tap controllers: one as part of the primary switch function and one to control the traditional jtag interface at the periphery of the device for manufacturing test purposes. configuration of the ds26900 is accomplished via the switch tap controller. configuration options include sensing the presence of secondary ports, addressing the target secondary port, reading/writing scratchpad registers, gpio pin read/write, generating port resets, configuring path and signaling inversion options , and placing the ds26900 in transparent mode for direct communications with the secondary por t. communications with the ds26900 is accomplished via a master port while asserting the as sociated ports configure signal ( trst1 , trst2, or ecfg ) low. connected ports (cards) are detected by sensing the ports tms pullup resistor, and the results are available in the port detection register ( pdr ). selection of the desired port is accomplished by setting the address in the secondary port selection register ( spsr ). once the destination p ort selection bits are written, the switch tap controller is returned to idle/reset state and the configuration signal ( trst ) is asserted high. the ds26900 routes the jtag signal set (clock, data - in, data - out, mode select, and reset) from the arbitrated master to the selected destination port with controlled timing relationships. a res et for the secondary port can be generated by writing a register bit after a port address is selected. test masters can be swapped without affecting the logic state of the selected secondary port. the ds26900 also contains traditional boundary scan circuitry at the periphery of the package for board manufacturing tests. see section 9 . this periphery boundary scan circuitry is independent and has priority over the operation of the master/slave multiplexer. it contains a separate tap controller with a 3 - bit wide instruction code register. signals associated with the periphery boundary scan circuitry are ptrst , ptms, ptck, ptdi, and ptdo . the ds26900 switch is designed to work at clock rates up to 50mhz. the arbitrated master is the source of the operating clock. however, the separate periphery jtag function, as described above, operates at a maximum frequency of 10mhz. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 20 4 . de t a ile d de sc ript i on 4 .1 mode s of ope ra tion the mode pins, m1 and m0, provide four modes of operation as described in table 4-1 . table 4-1 . mode pins m1 m0 mode of operation descr iption 0 0 single - package 18 secondary ports, tm1 and tm2 slave ports when configuration bit tm_slave set to logic 1. 0 1 cascade - master first group of 18 secondary ports, tm1 and tm2 are slave ports. 1 0 cascade - extension second group of 18 secondary p orts. 1 1 deselect device is deselected (acts as if no master is present). 4 .1 .1 single - pa c ka ge m ode single - package mode allows access to 18 or 20 secondary ports. see table 4-1 for m0 and m1 pin settings. if the tm_slave bit in the dcr register is set = 0, the device is configured for three master ports and 18 secondary ports, as shown in figure 4-1 . if the tm_slave bit in t he dcr register is set = 1, the device is configured for one master port and 20 secondary ports, as shown in figure 4-2. . in this configuration, tm1 and tm2 are used as secondary ports 19 and 20. if one or more master ports are unused, their req input pin(s) must be connected = v dd and the remaining unused inputs must be connected = v dd or v ss , but cannot be left unconnected . figure 4-1 . configuration for 3 masters, 18 secondary ports ds26900 etm tm1 tm2 secondary 1 secondary 18 pren m[1:0] = 00 vdd external test master test master 1 test master 2 6 6 6 5 5 instruction code = "0xxxx" figure 4-2 . configuration for 1 master, 20 secondary ports ds26900 etm secondary 1 secondary 18 pren m[1:0] = 00 vdd external test master 6 5 5 instruction code = "0xxxx" scr.tm_slave = 1 secondary 19 5 secondary 20 5 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 21 ds26900 etm tm1 tm2 secondary 1 secondary 18 pren m[1:0] = 10 (extension) m[1:0] = 01 (master) vdd external test master test master 1 test master 2 6 6 6 etm tm1 tm2 pren secondary 19 secondary 36 ds26900 5 5 5 5 instruction code = "0xxxx" instruction code = "1xxxx" 4 .1 .2 ca sc a de confi gurat ion m ode s the cascade configuration allows two devices to be connected together, the cascade master and the casc ade extension device. this provides access to 36 secondary ports plus the tm1 and t m2 ports (as slave ports) of the extension device without external control logic. the cascade master has its mode pins (m[1:0]) set = 01 a nd the cascade extension has its mode pins (m[1:0]) set = 10. see table 4-1 for m0 and m1 pin settings. in figure 4-3 , secondary ports 1 to 18 or 19 to 36 are selected by the msb of the instruction code. each device has a 5 - bit instruction register. the lower four lsbs have common definitions between the cascade devices, but the ms b of the 5 - bit instruction register acts as an address bit. instructions to be executed by the cascade master hav e their msb set to 0. instructions to be executed by the cascade extension have their msb set to 1. the same instruct ions are loaded into each device, but only the appropriate device (determined by the mode pin setting) executes the instruction. the pren pin on the cascade master is connected = v dd to enable internal pullup/down resistors. on the cascade extension device, pren is connected = v ss to disable internal pullup/down resistors. if one or more master ports are unused, their req input pin(s) must be connected = v dd and the remaining unused inputs must be connected = v dd or v ss , but cannot be left unconnected . figure 4-3 . two cascaded devices downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 22 4 .1 .3 de se le ct mode and re dunda ncy deselect mode allows multiple devices to be connected in parallel with the use of external logic contr olling the m[1:0] and pren pins. deselect mode is enabled when the mode pins (m[1:0]) are both set high. this internally forces the tmreq1 , tmreq2 , and ereq signals to go high, causing the ds26900 to act as though no active master is present. when both mode pins are set low via the external select logic, the devi ce is selected and operated in single - package mode. applications requiring device redundancy can be achieved by asserting ptrst low and hiz low. this causes outputs to become high impedance and disables the pullups and pulldowns. during normal operation, p trst is asserted low and hiz is asserted high. a device that is deselected (m[1:0] = 11) internally acts as if an arbitrat ed master is not present. the switch tap controller goes into test - logic - reset (and the instruction register is cleared). the other programmable registers are left unchanged. figure 4-4 . three cascaded devices using external select logic ds26900 etm tm1 tm2 secondary 1 secondary 18 pren m[1:0] = 00/11 vdd external test master test master 1 test master 2 6 6 6 etm tm1 tm2 pren secondary 1 secondary 18 ds26900 5 5 5 5 instruction code = "0xxxx" instruction code = "0xxxx" etm tm1 tm2 pren secondary 1 secondary 18 ds26900 5 5 instruction code = "0xxxx" m[1:0] = 00/11 m[1:0] = 00/11 mode select logic downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 23 4 .2 m a st e r arbit ra t ion the ds26900 can have one of three possible master po rts: external test master (etm), test master 1 (tm1), or test master 2 (tm2). the tm1 and tm2 ports can be bidirectional based on the state of the configuration bit tm_slave. an application, which has less than three masters, can use any combination of master ports. table 4-2 lists the possible signal configurations and arbitrations for master. in the table , blocked indicates that the jtag signals are ignored both to and from this port, slave indicates that this port is a target for the jtag master, master indicates the jtag signal source port, config indicates the configuration mode for the ds26900, and normal indicates normal jtag signal operation from master to slave. table 4-2 . master arbitration e r eq e cfg t mre q 1 tr s t1 t mre q 2 tr s t2 active master mode tm1 interface mode tm2 interface mode l l l x l x etm config blocked blocked l h l x l x etm normal blocked blocked l h l x h x etm normal blocked slave l h h x l x etm normal slave blocked l h h x h x etm normal slave slave h x l l l x tm1 config master blocked h x l h l x tm1 normal master blocked h x h x l l tm2 config slave master h x h x l h tm2 normal slave master h x h x h x none inactive slave slave note: slave mode of tm1 and tm2 is affected by the state of the configuration bit tm_ slave. l = connect = v ss ; h = connect = v dd ; x = dont care only one master is allowed at any time. a test master that is in slave mode has the sense of all the jtag signals reversed (outputs become inputs, inputs become outputs, and only tmreq does not change), and it functions identically to a secondary port. a test master that is blocked has its control si gnals ignored (the jtag outputs are blocked, jtag inputs are set to a constant logic level, tmreq is unaffected). since the tm ports lack a separate configuration signal, trst functions as the configuration signal. to avoid glitches on the output secondary ports, all the master signals (tms, tdi, tdo, and clk) should be set to logic 0 while switching the master to/from test master 1 or test master 2. the tm1/tm2 slave interface mode will additionally be a ffected by the state of the configuration bit tm_slave. if an active master is not present ( ereq , tmreq1 , and tmre q2 are all logic 1), the switch tap controller goes into test - logic - reset and the content of the instruction register is cleared. all other registers retain their values. the msb of the last instruction, before clearing, is always retained in a separate register unless global reset is asserted. the port whose address is in the secondary port selection register ( spsr ) is technically still selected, and that port will not be affected by the state of the dpdv bit in the device configuration register ( dcr ). if a different master becomes the active master, communications can resume with the port whose address i s in the secondary port selection register and whose instruction register msb is of the proper value. the secondary port selection register should be written with all zeros once communications with secondary ports is completed. a ds26900 in deselect mode disables detection of ereq , tmreq1 , and tmreq2, and the device therefore acts as if an active master is not present. deselect mode is selected when the mode pins (m[1:0]) are both asserted high. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 24 the master grant signals, mgnt0 , mgnt1 , and mgnt2, are generated by the master arbitrator. these signals are available to the appropriate master to indicate that it has control. the mci output is asserted low to indicate this possible conflict should more than one of the req signals be asserted low. an active signal indicates the active (selected) device by asserting act low. the act pin is asserted low under the conditions listed in table 4-3 . table 4-3 . ac t output states m1 pin m0 pin instruction register value is there an active master? a ct output 0 0 0xxxx yes 0 0 0 1xxxx yes 1 0 1 0xxxx yes 0 0 1 1xxxx yes 1 1 0 0xxxx yes 1 1 0 1xxxx yes 0 1 1 xxxxx x 1 x x xxxxx no 1 x = dont care 4 .2 .1 m issing t e st m a st er or u nuse d t est m ast e r port an unused or missing test master has its tmreq signal tied high by the user (ds26900 has a pullup on that input pin so the user can leave this pin unconnected), which puts that port into slave mode. 4 .2 .2 de te c t ion of t he pre senc e of sec onda ry ports the presence of secondary ports is detected by sensing the logic level present on t he stmsn signal (the stmsn signal on a port should have a pullup) on each secondary port and test master port. logic 1 is latched into the 20 - bit port detection register ( pdr ) for each pullup that is sensed. the stmsn and tmsn signals are sensed and the port detection register ( pdr ) is updated each time the switch tap controller passes out of the reset state. (tmsn signals can only be sensed on tm1/tm2 slave - mode ports.) 4 .2 .3 se le c t ion of the se condary port selection of the secondary port (slave) is accomplished by writing a 5 - bit address into the secondary port selection register ( spsr ). due to the star configuration, only one port can be selected at a time. ports that are not detected as being present by sensing the pullup on the secondary ports tms pin can still be selected, and the signals will be sent to that port. this 5 - bit secondary port selection address is complemented and used to generate the selected slave port indicator bits ( sspi [4:0]). these bits can be used as a visual indicator as to which slave port has been selected. once communications with a secondary port has been completed, the secondary port selection register ( spsr ) should be set to all zeros. if not, the selected port address will not respond to the dpdv bit of the device configuration register ( dcr ). this is true if an active master is present or no t. 4 .2 .4 m a st er port /sec onda ry port pat h t im ing de sc ript ion each of the arbitrated masters passes into a 3 x 1 multiplexer and then a 1 x 20 mu ltiplexer, such that any of the three possible masters can connect to any of the 20 possible secondary ports (18 secondary ports plus the test master ports when available). the test clock (tck), test mode select (tms), test data in (tdi ), and test data out downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 25 (tdo) signals can each be individually inverted by setting an optional configuration bit. figure 1-1 diagrams this path in a simple form. 4 .3 gpi o pins ge ne ra l - purpose i /o the general - purpose i/o (gpio) are bidirectional pins that offer the user the ability to output logic levels or read input logic levels. each gpio pin can be configured to output logic 1, logic 0, or to be an input. configuration of the gpio pins for write or read operation is accomplished by writing the gpio configuration and write regist er ( gpiocr ) bits. the reading the logic state of the gpio pins can be accomplished by accessing the 4 - bit gpio read register ( gpiorr ). pins that are configured for read mode read the input logic state in the register. pins that are confi gured for output mode read back the logic state for which those pins are configured. 4 .4 progra m m able pullup/pulldow n re sistors a hardware configuration pin (pren) is provided to enable/disable pull resistors on the input signal pins of the three masters. pren works such that when connected to v dd , the following signals have pull resistors enabled: tck1, tck2, etdi, etck, tms1, tms2 20k ? pulldown tdi1, tdi2, etdo, tdo1, tdo2 10k ? pullup trst1 , trst2 , ecfg , etms 10k ? pullup when connected to v ss , the pull resistors on the signals above are disabled. pren can be connected to v dd for single device implementations or for one of the devices in a multiple - device implementation. connecting pren to v dd on multiple devices, which are in parallel, would cause the pull resistors to be connected in parallel. this would have the undesirable effect of halving the pull - resistor values. 4 .5 signa l pa th configura tion inve rsions to help overcome possible timing issues, the jtag signal path timing can be modified i n limited ways in the d evice configuration register ( dcr ). signal path timing changes are global and, once set, they apply to all secondary ports until reconfigured. figure 1-1 diagrams the relative placement of the signal path modifier logic. there are several possible options: ? the test clock (tck) from the arbitrated master to a slave port can be inverted by sett ing the tcki bit. ? the test data from the arbitrated master to a slave port can be inverted by setting the tdii bit . ? the test data coming from the slave port to the arbitrated master can be inverted by setting the tdo i bit. ? the tms signal from the arbitrated master to a slave port can be inverted by setting the tms i bit. there is only one set of configuration bits. switching from port to port does not change the configuration bi ts. 4 .6 sw itc h configura tion by ex te rna l te st ma ste r the external test master (etm) has the highest priority in the master arbitration circui t, so asserting ereq low makes the etm the master. the etm accesses the configuration mode of the swit ch by asserting ereq low and ecfg low. access is then provided to the switch tap controller. while in configuration mode, the secondary s lave ports jtag signals are asserted low (except strstn signals, which are high) and do not toggle. in configuration mode, the master has access to the configuration registers in the switch tap contro ller. when ereq is asserted low and a secondary port selection register ( spsr ) address from 1 to 18 is selected, the selected secondary port jtag signal group follows the etm signals. the switch tap controller operates as an ieee 1149.1 tap controller. instructions can be written and regis ters written or read using the 1149.1 state diagram. the switch tap controller uses the inver ted ecfg signal as reset. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 26 it can also be reset by asserting etms high for at least six clock cycles. the switch ta p controller should be returned to the test - logic - reset or run - test/id le state before asserting ecfg high. to communicate with a particular secondary port, an address from 1 to 18 must be written into the 5 - bit secondary port selection register ( spsr ) during the configuration mode. this address does not change unless it is overwritten. however, toggling global rest ( rst ) sets the secondary port selection register ( spsr ) to 00000b. an address of 00000b in the secondary port selection register ( spsr ) (or any nonvalid port address) blocks communications to all slave ports. only one secondary port can be selected at a time. 4 .7 sw itc h configura tion by te st ma ste r 1 or te st ma ste r 2 the master arbitration circuit determines which test master has priority. test master 1 ( tm1) or test master 2 (tm2) configures the switch by asserting its tmreqn low and trstn low. access to the switchs configuration mode is accomplished by asserting trstn low. while in configuration mode, the secondary slave ports jtag signals are asserted low (except strstn signals, which are high) and do not toggle. in configuration mode, the master has access to the configuration registers in the switch tap controller in the ds26900. when treqn is asserted low and a secondary port selection register ( spsr ) address from 1 to 18 (34) is selected, the secondary port jtag signal group toggles normally and the arbitrated tes t master acts as the master. the switch tap controller operates as a ieee 1149.1 tap controller. instructions can be written and registers written or read using the 1149.1 state diagram. the switch tap controller uses the inverted trstn signal as reset. it can also be reset by asserting tmsn high for at least six clock cycles. the switch tap controller should be returned to the test - logic - reset or run - test/idle state before asserting trstn high. to communicate with a particular secondary port, an address from 1 to 18 must be written into the 5 - bit secondary po rt selection register ( spsr ) during the configuration mode. this address does not change unless it is overwritten. however, toggling global rest ( rst ) sets the secondary port selection register ( spsr ) to 00000b. an address of 00000b in the secondary port selection register ( spsr ) (or any nonvalid port address) blocks communications to all slave ports. only one secondary port can be selected at any time. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 27 5 . re se t s 5 .1 globa l re se t usa ge the global reset, rst pin, does not affect the state machine logic of the switch tap controller. the rst pin resets all other read and/or write registers. 5 .2 se c onda ry port re se ts the reset pins for secondary ports are always logic 1 unless the port_rst or the all_p orts_rst instruction is set in configuration mode. when the port_rst instruction is loaded, the valid ports strstn is asserted logic 0 for three master tclks before returning to logic 1. when the all_ports_rst instruction is loaded, all valid strstn signals are asserted logic 0 for three master tclks before returning to logic 1. when not in configuration mode, the secondary ports strstn signals are always logic 1. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 28 6 . configura t ion m ode configuration mode is used by a master to program the options in the ds26900 switch and to configure the address of the secondary port. configuration mode for the etm is accomplished when ereq and ecfg are both asserted low. while ereq and ecfg are asserted low, the secondary slave ports jtag signals are not allowed to toggle ( strstn can only be asserted low by the switch tap controller port reset instructions). in configuration mode, the master has access to the configuration tap controller in the ds26900. when ereq is asserted low and ecfg is asserted high, the jtag signal group toggles normally and the etm acts as the master. configuration mode for the test master 1 and test master 2 is accomplished when treqn and trstn are both asserted low. while tmreq and trstn are both asserted low, the jtag signal group remains static. in configuration mode, the master has access to the configuration tap controller in the ds26900. to set the target (slave) port, the port address must be written to the secondary port selection register ( spsr ). there is only one configuration mode for the ds26900. as a result, the master can set a configuration that remains valid for any master secondary port until reconfigured or rst is asserted low. 6 .1 sw itc h tap controlle r the switch tap controller is implemented as standard ieee 1149.1 tap controller. see section 9.2 and figure 9-2 . 6 .1 .1 sw it ch i nst ruc t ions table 6-1 . switch tap instruction codes instructions selected register single - package and cascade master instruction codes cascade extension instruction codes idcode id register ( idr ) 00000 10000 port_det port detection register ( pdr ) 00001 10001 port_sel secondary port selection register ( spsr ) 00010 10010 gpio_cfg gpio configuration and write register ( g piocr ) 00011 10011 gpio_read gpio read register ( gpiorr ) 00100 10100 config device configuration register ( dcr ) 00101 10101 scratch_1 scratchpad 1 register ( spr1 ) 00110 10110 scratch_2 scratchpad 2 register ( spr2 ) 00111 10111 port_rst port reset for a selected port 01000 11000 nop no operation 01001 C 01110 11001 C 11110 all_ports_rst global port tes t reset 01111 11111 when performing a register write, the current value of a register is shifted out while t he new register value is being shifted in. for read - only registers, some bit value must be shifted in (which is ignored) to shif t out the current r egister value. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 29 the msb of the instruction code acts as an address bit. when in cascade configuration, the cascade mast ers tdo output and port communications is enabled only when the instruction msb is 0. the cascade extensions t do output and port communications is enabled only when the instruction msb is 1. in single - package mode, tdo output and port communications is enabled only when the instruction msb is 0. 6 .1 .1 .1 idcode the idcode instruction allows access to the id register ( idr ). the idr register is an 8 - bit read - only register that contains the revision code for the ds26900 in the lower 4 bits and a fixed 4 - bit code in the upper 4 bits. this is identical to the revision code of the id code, which is used for the periphery boundary scan. the idr register is read - only. writes to this register are ignored. 6 .1 .1 .2 port _det the port_det instruction initiates the sensing of the presence of secondary ports and allows access to the 20 - bit port detection register ( pdr ). the process of port detection temporarily changes the stmsn bidirectional pin outputs to inputs, senses which ports read as logical 1 (ports should have a 10k ? resistiv e pullup on their stmsn pin and the ds26900 has a 20k ? pulldown), and saves the results to the pdr register. then the user must wait in the run - test - idle state for a period of time to allow the voltage on the stms pin to settle, typicall y 100ms. a 1 in a bit position indicates that logic 1 was sensed on that ports stms pin. however, due to implementation variables, logic 0 in a bit position does not necessarily imply that a device is not attached to that port (the port stms pin must have a pullup on stms in order to be sensed). the pdr register inputs are level sensitive and are sampled after the port_det instruction is loaded. the values in this register do not affect the operation of the ds26900. port detection works for single - package and the two - package cascade configuration. writes to this register are ignored. 6 .1 .1 .3 port _sel the port_sel instruction allows access to the 5 - bit read/write secondary port selection register ( spsr ). writing a value to this register selects a port with which to communicate. valid addresses are f rom 00001b (port one selected) to 10100b (tms2). addresses greater than 10100b and address 00000b do not select a port. selecting an empty or nonexistent port has no adverse effect on the device, and no secondary port signals will toggle. 6 .1 .1 .4 gpi o_cfg the gpio_cfg instruction allows access to the 8 - bit read/write gpio configuration and write register ( gpio cr ). the four gpio pins can be individually configured to be an input, output logic 1, or output logic 0. the values, which are sensed on the pins, are available in the gpio read register ( gpiorr ) via the gpio_read instruction. after global reset, the gpio configuration and write register ( gpiocr ) bits are set to 00000000b and the gpio pins are set to input mode. 6 .1 .1 .5 gpi o_read the gpio_read instruction allows access to the 4- bit read - only gpio read register ( gpiorr ). a 1 in a bit position indicates that logic 1 was sensed on that inputs gpio pin, and a 0 in a bit position indicates that logic 0 was sensed on that gpio pin. if a pin was configured as an output, the register bit indicates the value be ing output. writes to this register are ignored. the gpio inputs are level sensitive and are sampled after the gpio_read instruction is loaded. gp io pins that are configured as outputs are always read in this register as the value that is being output. after reset, the g pio read register ( gpiorr ) bits are set to 0000b until a gpio_read instruction is given. writes to this register are ignored. 6 .1 .1 .6 con fi g the config instruction allows access to the 6 - bit read/write device configuration register ( dcr ). the dcr register controls options such as path and signaling inversions and the default deselected port drive values. 6 .1 .1 .7 scrat ch _1 the scratch_1 instruction allows access to the 32 - bit read/write scratchpad 1 register ( spr1 ). the spr1 register is a user storage location, which is reset by the global reset signal. the values stored in this regi ster do not affect the operation of the ds26900. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 30 6 .1 .1 .8 scrat ch _2 the scratch_2 instruction allows access to the 32 - bit read/write scratchpad 2 register ( spr2 ). the spr2 register is a user storage location, which is reset by the global reset signal. the values stored in this r egister do not affect the operation of the ds26900. 6 .1 .1 .9 port _rst the port_rst instruction generates a port - specific strstn signal. port selection must first be performed by loading an address into the secondary port selection register ( spsr ). the selected strstn signal is asserted high, asserted low for three (tclk) clock periods, and then is asserted high. if the spsr register contains 00000b or an invalid address, no port reset is generated. the three -clock- period width is a fixed value. exit from configuration mode before th ree clock periods have elapsed can shorten the width of this pulse. 6 .1 .1 .1 0 n op the nop instruction is no operation. it does not perform a function. 6 .1 .1 .1 1 all_port s_rst the all_ports_rst instruction generates a strstn signal to all possible 18 (or 20) ports simultaneo usly. all strstn signals start by being asserted high, asserted low for three (tclk) clock periods , and then asserted high. the three -clock- period width is a fixed value. exit from configuration mode before three clock periods have elapsed can shorten the width of this pulse. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 31 7 . de vic e re gist e rs table 7-1 . ds26900 list of registers register name size (bits) function idr 8 device identification and revision code register dcr 6 device configuration register gpiocr 8 gpio configuration and write register gpiorr 4 gpio read register p dr 20 port detection register spsr 5 secondary port selection register spr1 32 scratchpad register 1 spr2 32 scratchpad register 2 reg ister name: idr register description: 8- bit device identification and revision code register bit # 7 6 5 4 3 2 1 0 name id7 id6 id5 id4 id3 id2 id1 id0 reset 1 1 0 0 revid[3] revid[2] revid[1] revid[0] bits 7 to 4: (id[7:4]) fixed binary pattern. bi ts 3 to 0: (id[3:0]). bit revision id. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 32 register name: dcr register description: 6- bit device configuration register bit # 7 6 5 4 3 2 1 0 name tm_slave dpdv tmsi tdii tdoi tcki reset 0 0 0 0 0 0 bit 5: test master slave enable (tm_slave). de termines in conjunction with m[1:0] if the ds26900 device will drive nonmaster tm1/tm2 as slaves. if the tm buses are in parallel with more than one ds26900, only one ds26900 can drive tm1/tm2 as a slave. the following table describes the combinations. mode m[1:0] tm_slave bit tm1/tm2 slave capable single - package 00 0 no single - package 00 1 yes cascade master 01 n/a yes cascade extension 10 n/a no deselect 11 n/a n/a bit 4: deselected port drive values (dpdv). this bit determines the logic levels driving a deselected secondary port according to the following table. note: this configuration bit does not apply to tm1 or tm2 in slave mode. tm1 or tm2 port signals in slave mode will never be high impedance. a secondary port is not selected (deselected) when device is in switch configur ation mode, or when the particular port address is not loaded in the secondary port selection register ( spsr ). the state of this bit can be monitored via the dpdv pin. signal dpdv = 0 dpdv = 1 stmsn 0 hiz * strstn 1 1 stdin 0 hiz * stckn 0 0 * hiz is a high - impedance state with no internal pullup/down resistors active. bit 3: test mode select invert (tmsi). invert the tms signal from the arbitrated master to the selected slave port by sett ing this bit to logic 1. bit 2: test data in invert (tdii). invert the tdi signal from the arbitrated master to the selected slave port by setting this bit to logic 1. bit 1: test data out invert (tdoi). invert the tdo signal from the selected slave port to the arbitrated master by setting this bit to logic 1. bit 0: test clock invert (tcki). invert the tck from the arbitrated master to the selected slave port by setting this bit to logic 1. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 33 register name: gpiocr register description: 8- bit gpio configura tion and write register bit # 7 6 5 4 3 2 1 0 name gpio3[1] gpio3[0] gpio2[1] gpio2[0] gpio1[1] gpio1[0] gpio0[1] gpio0[0] reset 0 0 0 0 0 0 0 0 bit 7: gpio3 configuration bit 1 (gpio3[1]) gpion[1] gpion[0] gpion pin mode 0 0 input 0 1 output logic 0 1 0 output logic 1 1 1 reserved bit 6: gpio3 configuration bit 0 (gpio3[0]) bit 5: gpio2 configuration bit 1 (gpio2[1]) bit 4: gpio2 configuration bit 0 (gpio2[0]) bit 3: gpio1 configuration bit 1 (gpio1[1]) bit 2: gpio1 configuration bit 0 (gpio1[0]) bit 1: gpio0 configuration bit 1 (gpio0[1]) bit 0: gpio0 configuration bit 0 (gpio0[0]) register name: gpiorr register description: 4- bit gpio read register bit # 7 6 5 4 3 2 1 0 name in[3] in[2] in[1] in[0] reset 0 0 0 0 bit 3: gp io3 input value (in[3]) bit 2: gpio2 input value (in[2]) bit 1: gpio1 input value (in[1]) bit 0: gpio0 input value (in[0]) downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 34 register name: pdr register description: 20 - bit port detection register (read - only) bit # 23 22 21 20 19 18 17 16 name port20 (tm2 slave) port19 (tm1 slave) port18 port17 reset 0 0 0 0 bit # 15 14 13 12 11 10 9 8 name port16 port15 port14 port13 port12 port11 port10 port9 reset 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name port8 port 7 port6 port5 port4 port 3 port2 port1 reset 0 0 0 0 0 0 0 0 bits 19 and 18: port detection (port[20:19]). if the tms signal on portn has a 10k ? pullup resistor, a value of 1 is recorded in the bit location corresponding to portn. the switch tap controller instruction port _det i nstruction triggers the port detection action. detection is also determined by the setti ngs of the m[1:0] pins and the tm_slave configuration bit. bits 17 to 0: port detection (port[18:1]). if the tms signal on portn has a 10k ? pullup resistor, a value of 1 is recorded in the bit location corresponding to portn. the switch tap controller instruction port_det instru ction triggers the port detection action. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 35 register name: spsr register description: 5- bit secondary port selection register bit # 7 6 5 4 3 2 1 0 name ssp[4] ssp[3] ssp[2] ssp[1] ssp[0] reset 0 0 0 0 0 bits 4 to 0: secondary port selection (ssp[4:0]). port address (see table 7-2 ). table 7-2 . secondary port selection bits and indicator pins ssp[4:0] bits selected port ss pi [4:0] pins 00000 no port selected 11111 00001 port 1 11110 00010 port 2 11101 00011 port 3 11100 00100 port 4 11011 00101 port 5 11010 00110 port 6 11001 00111 port 7 11000 01000 port 8 10111 01001 port 9 10110 01010 port 10 10101 01011 port 11 10100 01100 port 12 10011 01101 port 13 10010 01110 port 14 10001 01111 port 15 10000 10000 port 16 01111 10001 port 17 01110 10010 port 18 01101 10011 po rt 19* (tm1 slave mode) 01100 10100 port 20* (tm2 slave mode) 01011 10101 C 11111 no port selected 11111 * ports 19 and 20 are only available if tm1 and/or tm2 are available to be driven in slave mode. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 36 register name: spr1 register description: 32 - bit scratchpad register 1 bit # 31 30 29 28 27 26 25 24 name sr1[31] sr1[30] sr1[29] sr1[28] sr1[27] sr1[26] sr1[25] sr1[24] reset 0 0 0 0 0 0 0 0 bit # 23 22 21 20 19 18 17 16 name sr1[23] sr1[22] sr1[21] sr1[20] sr1[19] sr1[18] sr1[17] sr1[16] reset 0 0 0 0 0 0 0 0 bit # 15 14 13 12 11 10 9 8 name sr1[15] sr1[14] sr1[13] sr1[12] sr1[11] sr1[10] sr1[9] sr1[8] reset 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 name sr1[7] sr1[6] sr1[5] sr1[4] sr1[3] sr1[2] sr1[1] sr1[0] reset 0 0 0 0 0 0 0 0 bits 31 to 0 : scratchpad register 1 bits 31 to 0 (sr1[31:0]) register name: spr2 register description: 32 - bit scratchpad register 2 bit # 31 30 29 28 27 26 25 24 name sr2[31] sr2[30] sr2[29] sr2[28] sr2[27] sr2[26] sr2[25] sr2[24] reset bit # 23 22 21 20 19 18 17 16 name sr2[23] sr2[22] sr2[21] sr2[20] sr2[19] sr2[18] sr2[17] sr2[16] reset bit # 15 14 13 12 11 10 9 8 name sr2[15] sr2[14] sr2[13] sr2[12] sr2[11] sr2[10] sr2[9] sr2[8] reset bit # 7 6 5 4 3 2 1 0 name sr2[7] sr2[6] sr2[5] sr2[4] sr2[3] sr2[2] sr2[1] sr2[0] reset bits 31 to 0: scratchpad register 2 bits 31 to 0 (sr2[31:0]) downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 37 8 . addit iona l applic a t ion i nform a t ion 8 .1 ac ce ssing individua l de vice j tag on a boa rd the ds26900 can be used to provide access to individual device jtag chains on a board. for this configurati on, tmreq1 and tmreq2 are tied high and ereq is tied low, yielding a single - master configuration with a 5 - pin interface. individual subports on the ds26900 can be selected in configuration mode. 8 .2 using led i ndic a tors on the sspi , a ct a nd mc i pins led indicators can be attached to the mci, act, and/or sspi [4:0] pins by connecting the anode of the led to v dd via a series resistor and the cathode connected to the appropriate ds26900 pin. series resistance should be no less than approximately 175 ? to limit current to 8ma. 8 .3 using 2 .7 v and 1 .8v logic le ve ls w ith t he ds26 90 0 the ds26900 operates at a nominal supply voltage of 3.3v. the input buffers are designed to switch at midrail (v dd /2 = ~1.65v) with some hysteresis. this allows the input buffers the ability to sense 2.7v and 1.8v cmo s logic levels without modification or configuration in some applications. with that in mind, com patibility with 2.7v and 1.8v cmos logic levels (ot her than 3.3v cmos logic level) is not expressly guaranteed. the output buffers are ca pable of 3.3v cmos (rail - to - rail) logic levels. 8 .4 se rie s te rm ina tion re sistors although not part of the ieee 1149.1 specification, some pcb designs require series termination of clock s ignals at the electrical source. for the ds26900, the recommended typical series termination value for outputs i s 33 ? . this value can vary depending on the pcbs trace geometries. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 38 9 . pe riphe ry j t ag 9 .1 pe riphe ry j tag de sc ription the ds26900 contains traditional boundary scan circuitry at the periphery of the package for board manufacturing tests. this periphery boundary scan circuitry is independent and has priority over the oper ation of the master/slave multiplexer. it contains a separate tap controller with a 3 - bit wide instruction code register. signals associated with the periphery boundary scan circuitry are ptrst , ptms, ptck, ptdi, and ptdo. the ds26900 supports the standard instruction codes sample/preload, bypass, and extest. opti onal public instructions included are highz, clamp and idcode. see figure 9-1 for a block diagram. the ds26900 contains the following items, which meet the requirements set by the ieee 1149.1 standard test access port and boundary scan architecture: test access port (tap) tap controller instruction register bypass register boundary scan register device identification register details on the boundary scan architecture and the test access port can be found in ie ee 1149.1 - 2001, ieee 1149.1 - 1990, ieee 1149.1a - 1993, and ieee 1149.1b - 1994. figure 9-1 . periphery jtag block diagram boundary scan register identification register bypass register instruction register test access port controller mux select tri - state ptdi 10k ? ptms 10k ? ptclk ptrst 10k ? ptdo downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 39 9 .2 j tag tap controlle r sta te ma c hine de sc ription this section covers the details on the operation of the test access port (tap ) controller state machine. see figure 9-2 for details on each of the states described. the tap controller is a finite state machine that responds to the logic level at ptms on the rising edge of ptclk. figure 9-2 . jtag tap controller state machine test - logic - reset. upon device power - up, the tap controller starts in the test - logic - reset state. the instruction register contains the idcode instruction. all system logic on the device operates normally. run - test - idle. run - test - idle is used between scan operations or during specific tests. the instruction register and test register remain idle. select - dr - scan. all test registers retain their previous state. with ptms low, a ri sing edge of ptclk moves the controller into the capture - dr state and initiates a scan sequence. ptms high moves the controller to the sel ect - ir - scan state. capture - dr. data can be parallel loaded into the test data registers selected by the current instructi on. if the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test regi ster test - logic - reset run - test/idle select dr - scan 1 0 capture - dr 1 0 shift - dr 0 1 exit1 - dr 1 0 pause - dr 1 exit2 - dr 1 update - dr 0 0 1 select ir - scan 1 0 capture - ir 0 shift - ir 0 1 exit1 - ir 1 0 pause - ir 1 exit2 - ir 1 update - ir 0 0 1 0 0 1 0 1 0 1 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 40 remains at its current value. on the rising edge of ptclk, the controller goes to t he shift - dr state if ptms is low or it to the exit1 - dr state if ptms is high. shift- dr. the test data register selected by the current instruction is connected between ptdi and ptdo and shifts data one stage towards its serial output on each rising edge of ptclk. if a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. exit1- dr. while in this state, a rising edge on ptclk with ptms high puts the controller in the update - dr state, wh ich terminates the scanning process. a rising edge on ptclk with ptms low puts the controller in the pause - dr state. pause - dr. shifting of the test registers is halted while in this state. all test registers selected by the c urrent instruction retain their previous state. the controller remains in this state while ptms is low. a rising edge on ptclk with ptms high puts the controller in the exit2 - dr state. exit2- dr. while in this state, a rising edge on ptclk with ptms high puts the controll er in the update - dr state and terminates the scanning process. a rising edge on ptclk with ptms low puts the controller in the shift - dr state. update - dr. a falling edge on ptclk while in the update - dr state latches the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output due to changes in the shift register. a rising edge on ptclk with ptms low puts the controller in the run - test - idle state. with ptms high, the controller enters the select - dr - sca n state. select - ir - scan. all test registers retain their previous state. the instruction register remains unchanged during this state. with ptms low, a rising edge on ptclk moves the controller into the capt ure - ir state and initiates a scan sequence for the instruction register. ptms high during a rising edge on ptclk puts the controller back into t he test - logic - reset state. capture - ir. the capture - ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of ptclk. if ptms is high on the rising edge of ptclk, the controller enters the exit1- ir state. if ptms is low on the rising edge of ptclk, the controller enters the shift - ir state. shift- ir. in this state, the shift register in the instruction register is connected between ptdi and ptdo and shifts data one stage for every rising edge of ptclk towards the serial output. the parallel register, as well as all test registers, remains at its previous states. a rising edge on ptclk with ptms high moves the cont roller to the exit1 - ir state. a rising edge on ptclk with ptms low keeps the controller in the shift - ir state while moving data one stage through the instruction shift register. exit1- ir. a rising edge on ptclk with ptms low puts the controller in the pause - ir state. if ptms is high on the rising edge of ptclk, the controller enters the update - ir state and terminates the scanning process. pause - ir. shifting of the instruction register is halted temporarily. with ptms high, a rising edge on ptclk puts the controller in the exit2 - ir state. the controller remains in the pause - ir state if ptms is low during a rising edge on ptclk. exit2- ir. a rising edge on ptclk with ptms high put the controller in the update - ir state. the controller loops back to the shift - ir state if ptms is low during a rising edge of ptclk in this state. update - ir. the instruction shifted into the instruction shift register is latched into the parallel output on the falling edge of ptclk as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on ptclk with ptms low, puts the controller in the run - test - idle state. with ptms high, the controller enters the select - dr - scan state. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 41 9 .3 j tag i nstruc tion re giste r a nd i nstruc t ions the instruction register contains a shift register as well as a latched parallel output and is 3 bits in l ength. when the tap controller enters the shift - ir state, the instruction shift register is connected between ptdi and ptdo. w hile in the shift - ir state, a rising edge on ptclk with ptms low shifts data one stage towards the serial output at ptdo. a rising edge on ptclk in the exit1 - ir state or the exit2 - ir state with ptms high moves the controller to the update - ir state. the falling edge of that same ptclk latches the data in the instruction shift register to the instruction parallel output. instructions supported by the ds26900 and their respective operational binary codes are shown in table 9-1 . table 9-1 . periphery jtag instruction codes instructions selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcode device identification 001 9 .3 .1 sam ple/preload this is a mandatory instruction for the ieee 1149.1 specification. this instruction supports two functions. t he digital i/os of the device can be sampled at the boundary scan register without interfering with the normal operat ion of the device by using the capture - dr state. sample/preload also allows the ds26900 to shift data into the boundary scan register via ptdi using the shift - dr state. 9 .3 .2 ex t est extest allows testing of all interconnections to the device. when the extest instruction is latched in the instruction register, the following actions occur. once enabled via the update - ir state, the parallel outputs of all digital output pins are driven. the boundary scan register is connected between ptdi and ptdo. the capture - dr samples all digital inputs into the boundary scan register. 9 .3 .3 by pass when the bypass instruction is latched into the parallel instruction register, ptdi connects to ptdo through the 1- bit bypass test register. this allows data to pass from ptdi to ptdo not affecting the devic e's normal operation. 9 .3 .4 idcode when the idcode instruction is latched into the parallel instruction register, the identificati on test register is selected. the device identification code is loaded into the identification register on the rising edge of ptclk following entry into the capture - dr state. shift - dr can be used to shift the identification code out serially via ptdo. during test - logic - reset, the identification code is forced into the instruction register's parallel output. the device id code always has a one in the lsb position. the next 11 bits identify t he manufacturer's jedec number and number of continuation bytes followed by 16 bits for the device and 4 bits for the v ersion. the device id code for the ds26900 is 0008d143. 9 .3 .5 h i gh z all digital outputs are placed into a high - impedance state. the bypass register is connected between ptdi and ptdo. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 42 9 .3 .6 clam p all digital outputs pins output data from the boundary scan parallel output while connecting the bypass register betw een ptdi and ptdo. the outputs do not change during the clamp instruction. 9 .4 j tag te st re giste rs ieee 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. an optional test register has been included in the device design. this test register is t he identification register, and is used in conjunction with the idcode instruction and the test - logic - reset state of the tap controller. 9 .4 .1 bypa ss re gist er this is a single 1 - bit shift register used in conjunction with the bypass, clamp, and highz instructions, which provides a short path between ptdi and ptdo. 9 .4 .2 i de nt ific at ion regist er the identification register contains a 32 - bit shift register and a 32 - bit latched parallel output. this register is selected during the idcode instruction and when the tap controller is in the test - logic - reset state. 9 .4 .3 bounda ry sc a n regist e r this register contains both a shift register path and a latched parallel output for all contr ol cells and digital i/o cells and is 361 bits in length. downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 43 1 0 . ope ra t ing pa ra m e t e rs absolute maximum ratings voltage range on any lead with respect to v ss (except v dd ) .. - 0.3v to 5.5v supply voltage range (v dd ) with respect to v ss ..- 0.3v to 3.63v operating temperature range .- 40 c to +85 c storage temperature range ..- 55 c to +126 c lead temperature (soldering, 10s) .... +300 c soldering temperature (reflow) .. +260 c this is a stress rating only and functional operation of the device at these or a ny other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxim um rating conditions for extended periods of time may affect reliability. 1 0 .1 the rm a l i nform a tion table 10 -1 . thermal characteristics parameter value target ambient temperature range - 40 c to +85 c die junction temperature range - 40 c to +126 c theta - jc (junction to top of case) 10 c/w theta - jb (junction to bottom pins) 10 c/w theta - ja, still air 22 c/w (note 1) theta -ja 100 lfm 20 c/w (note 1) 200 lfm 17 c/w (note 1) 500 lfm 15 c/w (note 1) note 1: theta - ja values are estimates using jedec - standard pcb and enclosure dimensions. 1 0 .2 dc cha ra c te ristic s table 10 -2 . recommended dc operating conditions (t a = - 40 c to +85 c) parameter symbol min typ max units logic 1 v ih 2.4 4.2 v logic 0 v il - 0.3 0.8 v supply (v dd ) v dd 3.135 3.465 v table 10 -3 . dc electrical characteristics (v dd = 3.3v 5%, t a = - 40 c to +85 c.) parameter symbol min typ max u nits supply current (v dd = 3.465v) i dd 15 ma lead capacitance c io 7 pf input leakage i il - 10 +10 a input pins with internal pullup resistors i ilp - 250 +10 a output current (2.4v) i oh - 4.0 ma output voltage (i oh = -4.0ma) v oh 2.4 v output voltage (i oh = +4.0ma) v ol 0.4 v output current (0.4v) i ol +4.0 ma downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 44 1 1 . ac t im ing unless otherwise noted, all timing numbers assume 20pf test load on output signals, 40pf test load on bus signals. 1 1 .1 sw itc h tap controlle r i nte rfa ce tim ing table 11 -1 . switch tap controller interface timing (v dd = 3.3v 5%, t a = - 40 c to +85 c.) (see figure 11 -1 .) parameter symbol min typ max units notes etck, tck1, tck2 clock period t1 25 ns 30% dc etck, tck1, tck2 clock low time t2 17.5 ns etck, tck1, tck2 clock high time t3 7.5 ns etck to etdi, etms setup time tck1 to tdi1, tms1 setup time tck2 to tdi2, tms2 setup time t4 3 ns etck to etdi, etms hold time tck1 to tdi1, tms1 hold time tck2 to tdi2, tms2 hold time t5 3 ns etck to etdo delay tck1 to tdo1 delay tck2 to tdo2 delay t6 15 ns etck to etdo high - impedance delay tck1 to tdo1 high - impedance delay tck2 to tdo2 high - impedance delay t7 17.5 ns no te 1: tck should be stopped low. note 2: interface timing in table 11 -1 is to/from the arbitrated master. note 3: tck corresponds to each master port clock when being used to configure the cor e jtag con troller, e.g., etck or tck1 or tck2. note 4: tdi, tms correspond to the master port tdi, tms when being used to configur e the core jtag controller, e.g., etdi, etms or tdi1, tms1 or tdi2, tms2. note 5: tdo corresponds to the master port tdo when being us ed to configure the core jtag controller, e.g., etdo or tdo1 or tdo2. note 6: the configuration signals ( trst1 , trst2 , ecfg) and the master request signals ( tmreq1 , tmreq2 , ereq) are asynchronous. tck, tdi, tms should be low when switching masters to avoid the possibilit y of glitching the secondary port whose address is in the secondary port selection register ( spsr ). another method to avoid glitching the secondary port is to set the se condary port selection register ( spsr ) to 00000 when changing the arbitrated master. figure 11 -1 . switch tap controller interface timing diagram etck tck1 tck2 etdo tdo1 tdo2 t2 t3 t1 t4 etdi, etms tdi1, tms1 tdi2, tms2 t5 t6 t7 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 45 1 1 .2 tra nspa rent mode ma ste r/sla ve port t im ing table 11 -2 . master/slave port timing (v dd = 3.3v 5%, t a = - 40 c to +85 c.) (see figure 11 -2 .) parameter symbol min typ max units notes etck, t clk1, tclk2 to stckx latency etms, tms1, tms2 to stmsx latency etdi, tdi1, tdi2 to stdix latency t1 3 11 ns 1 etck, tclk1, tclk2 to stckx skew etms, tms1, tms2 to stmsx skew etdi, tdi1, tdi2 to stdix skew t2 0.8 4.0 ns 2, 3 stdox to etdo, tdo1, tdo2 la tency t3 3 11 ns 4 tdo + tck t5 11.4 16 26.4 ns 5 note 1: delay (latency) from a particular master port signal to the correspondin g slave port signal. note 2: skew values are with respect to a signal from the arbitrated master to the s ame signal on the selected secondary slave port. note 3: skew from any set of two signals at a master port to the corresp onding two signals at the selected slave port. note 4: delay path from a selected slave port stdo to the arbitrated masters t do. note 5: half - cycl e path from falling edge stck/stdo (launch) to rising edge tck/tdo (captur e), pass - through path (see figure 11 -2 ). note 6: tck corresponds to each master port clock when being used to configure the cor e jtag controller, e.g., etck or tck1 or tck2. tdi, tms correspond to the master port tdi, tms, e.g., etdi, etms or t di1, tms1 or tdi2, tms2. tdo corresponds to the master port tdo when being used to configure the core jtag controller, e.g. , etdo or tdo1 or tdo2. note 7: stck corresponds to each slave port clock, e.g., stck1 C stck18. stdi, stms correspond to the slave port tdi, tms, e.g., stdi1 C stdi18, stms1 C stms18. stdo corresponds to the slave port stdo1 C stdo18. figure 11 -2 . transparent mode master/slave port timing diagram etck, tck1, tck2 etms, tms1, tms2 etdi, tdi1, tdi2 stckn, stmsn, stdin stdon etdo, tdo1, tdo2 t5 t1 t2 t3 t4 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 46 1 1 .3 pe riphe ry j tag i nte rfa c e tim ing table 11 -3 . periphery jtag interface timing (v dd = 3.3v 5%, t a = - 40 c to +85 c.) (see figure 11 -3 .) parameter symbol min typ max units notes ptclk clock period t1 100 ns 1 ptclk clock high/low time t2/t3 30 ns 2 ptclk to ptdi, ptms setup time t4 20 ns ptclk to ptdi, pt ms hold time t5 10 ns ptclk to ptdo delay t6 2 10 ns ptclk to ptdo high - impedance delay t7 2 10 ns ptrst width low time t8 50 ns note 1: clock period for the periphery boundary scan is 100ns (min). note 2: clock can be stopped high or low . figure 11 -3 . periphery jtag interface timing diagram ptclk ptdo t2 t3 t1 t4 ptdi ptms t5 t6 t7 t8 ptrst downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 47 1 2 . pin configura t ion downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 48 1 3 . pa c k a ge i nform a t ion for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 144 lqfp c144l+5 21 - 0299 90 - 0296 downloaded from: http:///
__________________________________________________ ________________________________________ ds2 6 9 00 maxim cannot assume responsibility for use of any circuitry other than cir cuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specificat ions without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 49 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products. 1 4 . doc um e nt re vision h ist ory revision number revision date description pages changed 0 072707 initial release 1 2/11 part number in ordering information t able changed from ds26900n+ to DS26900LN+ 1 downloaded from: http:///

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